semiconductor msc23v13258d-xxbs2 1,048,576-word x 32-bit dynamic ram module : fast page mode type with edo this version: apr. 13. 1999 description the msc23v13258d-xxbs2 is an 1,048,576-word x 32-bit cmos dynamic random access memory module which is composed of two 16mb(1mx16) drams in tsop packages mounted with two decoupling capacitors. this is an 100-pin dual in-line memory module. this module supports any application where high density and large capacity of storage memory are required. features 1,048,576-word x 32-bit organization 100-pin dual in-line memory module gold tab single 3.3v power supply, 0.3v tolerance input : lvttl compatible output : lvttl compatible, 3-state refresh : 1024cycles/16ms /cas before /ras refresh, hidden refresh, /ras only refresh capab ility fast page mode with edo, read modify write capab ility dq pins have 10ohm series resistor serial presence detect product family access time (max.) power dissipation (max.) family t rac t aa t cac t oea cycle time (min.) operating standby msc23v13258d-50bs2 50ns 25ns 13ns 13ns 84ns 900mw MSC23V13258D-60BS2 60ns 30ns 15ns 15ns 104ns 828mw msc23v13258d-70bs2 70ns 35ns 20ns 20ns 124ns 756mw 3.6mw
semiconductor msc23v13258d module outline 150 r1.0 19.050.1 6.35 0.1 84.17 typ. 90.19typ. 4.0min. 2.7max. (unit : mm) msc23 v13258d -xxbs 2 2 - r2.0 0.1 2 - f 3.00.1 1.27 0.1 2.0 0.1 3.120.13 1.270.1 0.23min. 1.0 0.1 0.20 6.350.1 detail a 34.290.1 17.800.13 3.00.13 2.0 0.1 6.350.1 detail b 3.120.13 detail c a b c 25.40 0.13 4.175 0.13 3.175 0.13 88.19 0.2 90.19 0.2 r1.0 2.50
semiconductor msc23v13258d pin configuration front side back side front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 51 v ss 26 v ss 76 v ss 2dq052dq827nc77nc 3 dq1 53 dq9 28 /we 78 /oe 4 dq2 54 dq10 29 /ras0 79 nc 5 dq3 55 dq11 30 /ras2 80 nc 6v cc 56 v cc 31 v cc 81 v cc 7 dq4 57 dq12 32 nc 82 nc 8 dq5 58 dq13 33 nc 83 nc 9 dq6 59 dq14 34 nc 84 nc 10 dq7 60dq1535 nc 85 nc 11 /cas0 61 /cas1 36 v ss 86 v ss 12 v ss 62 v ss 37 /cas2 87 /cas3 13 a0 63 a1 38 dq16 88 dq24 14 a2 64 a3 39 dq17 89 dq25 15 a4 65 a5 40 dq18 90 dq26 16 a6 66 a7 41 dq19 91 dq27 17 a8 67 a9 42 v cc 92 v cc 18 nc 68 nc 43 dq20 93 dq28 19 nc 69 nc 44 dq21 94 dq29 20 nc 70 nc 45 dq22 95 dq30 21 v cc 71 v cc 46 dq23 96 dq31 22 nc 72 nc 47 v ss 97 v ss 23 nc 73 nc 48 sda 98 sa0 24 nc 74 nc 49 scl 99 sa1 25 nc 75 nc 50 v cc 100 sa2
semiconductor msc23v13258d serial pd matrix byte no. function described spd value (hex) note 0 number of byte used 80 128 bytes 1 total spd memory size 08 256 bytes 2 memory type 02 edo 3 number of rows 0a 10 4 number of columns 0a 10 5 number of banks 01 1 6 module data width 20 32 7 module data width continued 00 0 8 supply voltage 01 lvttl -50 32 50ns -60 3c 60ns 9 -70 /ras access time 46 70ns -50 0d 13ns -60 0f 15ns 10 -70 /cas access time 14 20ns 11 dimm configuration type 00 non-parity 12 refresh rate/type 00 normal refresh 13 primary dram width 10 x16 14 error checking dram width 00 15-61 superset information 00 reserved 62 spd data revision code 01 1 -50 10 -60 1c 63 -70 checksum for byte 0-62 2b 64-127 reserved 00 128-255 unused storage location (reserved) ff
semiconductor msc23v13258d block diagram /ras0 /we /oe dq0 dq1 dq2 dq3 /cas0 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 /cas1 dq12 dq13 dq14 dq15 dq1 dq3 dq2 dq4 /ras /we /oe d0 dq5 dq7 dq6 dq8 /lcas dq9 dq11 dq10 dq12 dq13 dq15 dq14 dq16 /ucas /ras2 dq16 dq17 dq18 dq19 /cas2 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 /cas3 dq28 dq29 dq30 dq31 dq1 dq3 dq2 dq4 /ras /we /oe d1 dq5 dq7 dq6 dq8 /lcas dq9 dq11 dq10 dq12 dq13 dq15 dq14 dq16 /ucas v cc v ss c1-c2 a0-a9 a0-a9 : d0-d1 d0-d1 d0-d1 scl sda a0 a1 a2 scl sda sa0 sa1 sa2 serial pd note: all resistors values are 10ohms
semiconductor msc23v13258d electrical characteristics absolute maximum ratings parameter symbol rating unit voltage on any pin relative to v ss v in , v out -0.5 to 4.6 v voltage on v cc supply relative to v ss v cc -0.5 to 4.6 v short circuit output current i os 50 ma power dissipation p d *2w operating temperature t opr 0 to 70 c storage temperature t stg -40 to 125 c * ta = 25c recommended operat ing conditions ( ta = 0c to 70c ) parameter symbol min. typ. max. unit v cc 3.0 3.3 3.6 v power supply voltage v ss 000v input high voltage v ih 2.0 - v cc +0.3 v input low voltage v il -0.3 - 0.8 v capacitance ( v cc = 3.3v 0.3v, ta = 25c, f = 1 mhz ) parameter symbol typ. max. unit input capacitance (a0 - a9) c in1 -16pf input capacitance (/ras0, /ras2) c in2 -13pf input capacitance (/cas0 - /cas3) c in3 -13pf input capacitance (/we) c in4 -20pf i/o capacitance (dq0 - dq31) c i/o -13pf
semiconductor msc23v13258d dc characteristics (v cc = 3.3v 0.3v, ta = 0c to 70c ) -50 -60 -70 parameter symbol condition min. max. min. max. min. max. unit note output high voltage v oh i oh = -2.0ma 2.4 v cc 2.4 v cc 2.4 v cc v output low voltage v ol i ol = 2.0ma 0 0.4 0 0.4 0 0.4 v input leakage current i li 0v v in v cc +0.3v; all other pins not under test = 0v -20 20 -20 20 -20 20 m a output leakage current i lo dq disable 0v v out v cc -10 10 -10 10 -10 10 m a average power supply current (operating) i cc1 /ras, /cas cycling, t rc = min. - 250 - 230 - 210 ma 1, 2 /ras, /cas = v ih -4-4-4ma power supply current (standby) i cc2 /ras, /cas 3 v cc -0.2v -1-1-1ma 1 average power supply current (/ras only refresh) i cc3 /ras cycling, /cas = v ih , t rc = min. - 250 - 230 - 210 ma 1, 2 average power supply current (/cas before /ras refresh) i cc6 /ras cycling, /cas before /ras - 250 - 230 - 210 ma 1, 2 average power supply current (fast page mode) i cc7 /ras = v il , /cas cycling, t hpc = min. - 250 - 230 - 210 ma 1, 3 notes: 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while /ras = v il . 3. the address can be changed once or less while /cas = v ih .
semiconductor msc23v13258d ac characteristics (1/2) (v cc = 3.3v 0.3v, ta = 0c to 70c ) note: 1, 2, 3 -50 -60 -70 parameter symbol min. max. min. max. min. max. unit note random read or write cycle time t rc 84 - 104 - 124 - ns read modify write cycle time t rwc 110 - 135 - 160 - ns fast page mode cycle time t hpc 20 - 25 - 30 - ns fast page mode read modify write cycle time t hprwc 58 - 68 - 78 - ns access time from /ras t rac -50-60-70ns4, 5, 6 access time from /cas t cac -13-15-20ns4, 5 access time from column address t aa -25-30-35ns4, 6 access time from /cas precharge t cpa -30-35-40ns4 access time from /oe t oea -13-15-20ns4 output low impedance time from /cas t clz 0-0-0-ns4 data output hold after /cas low t doh 5-5-5-ns /cas to data output buffer turn-off delay time t cez 013015020ns7, 8 /ras to data output buffer turn-off delay time t rez 013015020ns7, 8 /oe to data output buffer turn-off delay time t oez 013015020ns7 /we to data output buffer turn-off delay time t wez 013015020ns7 transition time t t 150150150ns3 refresh period t ref -16-16-16ms /ras precharge time t rp 30 - 40 - 50 - ns /ras pulse width t ras 50 10k 60 10k 70 10k ns /ras pulse width (fast page mode with edo) t rasp 50 100k 60 100k 70 100k ns /ras hold time t rsh 7 - 10 - 13 - ns /ras hold time referenced to /oe t roh 7 - 10 - 13 - ns /cas precharge time (fast page mode with edo) t cp 7 - 10 - 10 - ns /cas pulse width t cas 7 10k 10 10k 13 10k ns /cas hold time t csh 35 - 40 - 45 - ns /cas to /ras precharge time t crp 5-5-5-ns /ras hold time from /cas precharge t rhcp 30 - 35 - 40 - ns /oe hold time from /cas (dq disable) t cho 5-5-5-ns /ras to /cas delay time t rcd 11 37 14 45 14 50 ns 5 /ras to column address delay time t rad 9 2512301235 ns6 row address set-up time t asr 0-0-0-ns row address hold time t rah 7 - 10 - 10 - ns column address set-up time t asc 0-0-0-ns column address hold time t cah 7 - 10 - 13 - ns column address to /ras lead time t ral 25 - 30 - 35 - ns
semiconductor msc23v13258d ac characteristics (2/2) (v cc = 3.3v 0.3v, ta = 0c to 70c ) note: 1, 2, 3 -50 -60 -70 parameter symbol min. max. min. max. min. max. unit note read command set-up time t rcs 0-0-0-ns read command hold time t rch 0-0-0-ns9 read command hold time referenced to /ras t rrh 0-0-0-ns9 write command set-up time t wcs 0-0-0-ns10 write command hold time t wch 7 - 10 - 13 - ns write command pulse width t wp 7 - 10 - 10 - ns /we pulse width (dq disable) t wpe 7 - 10 - 10 - ns /oe command hold time t oeh 7 - 10 - 13 - ns /oe precharge time t oep 7 - 10 - 10 - ns /oe command hold time t och 7 - 10 - 10 - ns write command to /ras lead time t rwl 7 - 10 - 13 - ns write command to /cas lead time t cwl 7 - 10 - 13 - ns data-in set-up time t ds 0-0-0-ns data-in hold time t dh 7 - 10 - 13 - ns /oe to data-in delay time t oed 13 - 15 - 20 - ns /cas to /we delay time t cwd 30 - 34 - 44 - ns 10 column address to /we delay time t awd 42 - 49 - 59 - ns 10 /ras to /we delay time t rwd 67 - 79 - 94 - ns 10 /cas precharge /we delay time t cpwd 47 - 54 - 64 - ns 10 /cas active delay time from /ras precharge t rpc 5-5-5-ns /ras to /cas set-up time (/cas before /ras) t csr 5-5-5-ns /ras to /cas hold time (/cas before /ras) t chr 10 - 10 - 10 - ns
semiconductor msc23v13258d notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles (/ras only refresh or /cas before /ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 2ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 1 ttl load and 100pf. the output timing reference levels are v oh = 2.0v and v ol = 0.8v. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t cez (max.), t rez (max.), t wez (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t cez or t rez must be satisfied for open circuit condition. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd , t aw d and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.), t rwd 3 t rwd (min.), t aw d 3 t aw d (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data r ead from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
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